Electronic memory is widely used in consumer and commercial applications. The different types of electronic memory are broadly classified as volatile or non-volatile. Volatile memory includes SRAM and DRAM and is advantageous because it provides fast reading and writing operations (SRAM) and high density (DRAM). Volatile memory suffers from the disadvantage, however, that its data content is lost when the memory is powered down. Non-volatile memory, in contrast, retains its data when powered down. Non-volatile memory includes EPROM, EEPROM, and Flash. As markets have expanded, volatile and non-volatile memories have evolved to address different application needs. Volatile memory is preferred in applications in which speed or endurance is a premium, while non-volatile memory has been emphasized in applications where persistent data retention without a need to restore or refresh data is important.
Electronic memory is frequently configured as an array that includes a set of bit lines and a set of word lines with a memory cell disposed between each bit line and each word line. Bit lines may also be referred to as column lines and word lines may also be referred to as row lines. The memory cell includes at least an active memory material that is capable of being electrically converted between two or more distinguishable memory states and typically further includes an access device to uniquely address a memory element, such as a transistor or diode, in series with the memory element material to regulate electrical access to the memory material and minimize leakage current when deselected. The array is operated by applying an addressing scheme to select a targeted memory cell for an access operation (read, write, erase). The addressing scheme typically involves selective application of a pattern of bias voltages to the bit lines and word lines of the array. The bit lines and word lines of unselected cells are typically held at a reference voltage, while the voltage of the bit line and/or word line of the selected cell is/are raised or lowered relative to the reference voltage to bias the flow of current through the selected cell to achieve the desired access operation.
Flash memory is presently the higher volume non-volatile electronic memory technology. The flash memory cell is based on a floating-gate MOS transistor. The flash cell includes source and drain regions formed in a substrate and a gate structure that includes a floating gate and control gate. The floating gate is positioned above the substrate and separated from the substrate by a tunnel oxide. The control gate is positioned above the floating gate and separated from it by a dielectric. The floating gate is complete surrounded by dielectric materials and capacitively controlled by the control gate. Since the floating gate is electrically isolated, it can store charge and the separate memory states of the flash cell are defined according to the amount of charged stored at the floating gate. The different charge states of the floating gate influence the voltage needed at the control gate to turn on the transistor. The threshold voltage of the transistor changed by writing to the cell, is determined by measuring current when the voltage is applied to the control gate, and becomes the metric by which the different memory states of the flash cell are distinguished. The threshold voltage, in turn, is a manifestation of the amount of charge stored (programmed or injected) on the floating gate.
The architecture and layout of flash cells in an array can be varied and used to define different forms of flash memory. NOR flash and NAND flash are the prevailing forms of flash in today's market. NAND flash is a high-volume technology that is optimized for large data storage applications, while NOR flash is a more specialized and more versatile technology that is directed to both code storage applications. Much of the recent growth in the adoption of Flash memory has occurred because of its successful implementation into portable electronic devices. Flash memory is widely used in cell phones, cameras, media players, and mobile computing and has proven to be a reliable commercial technology.
Expansion of flash memory volume has been assisted by an evolution and lowering of flash memory cost in the transition from single bit to multilevel operation. This evolution has significantly increased the data storage density of flash memory and has made a number of compact product applications possible. One factor underlying multilevel operation of flash memory (especially NAND flash) is a robust error correction capability. Flash memory cells are potentially subject to a number of errors that affect data integrity. The different errors may be collectively referred to as “bit” errors and for simplicity, the individual memory cells may be referred to as “bits”. Bit errors may originate from access operations, configuration defects in the array, or a combination of the two. Errors originating from access operations occur through errors in the access protocol or when a correct access protocol induces unintended effects in the array. Configuration defects are structural defects and include problems such as short circuits and open circuits caused by defects in the memory elements in the array or addressing and drive elements (transistors, diodes, and interconnect). Configuration defects may occur at the time of manufacture or develop over time through use of the array. Bit errors include write errors, write-disturb errors, data retention errors (caused by leakage of charge from the floating gate), read errors, and read-disturb errors. As the number of states utilized in flash memory increases, the detection margin for the different states narrows and the technology becomes more susceptible to errors and the need to correct errors becomes more pressing.
Error correction capability is typically provided by the controller used to operate flash memory. Most error correction schemes involve the use of check data bits dedicated to error correction and an error correction algorithm. The check data bits are redundant bits that are included in the memory array and represent chip overhead that needs to be minimized. Popular error correction algorithms include the Hamming code, the Bose-Chaudhiri-Hocquenghem (BCH) code (NAND), the Reed-Solomon (RS) code (NAND), and the trellis coded modulation (TCM) (NOR). Information on implementation of error correction codes in flash memory can be found in Gregori, S. et al., “On-Chip Error Correcting Techniques for New Generation Flash Memories”; Proc. IEEE 91(4) 602-616 (2003).
As efforts toward chip miniaturization continue, the scaling of flash memory to smaller dimensions is becoming increasingly problematic. Problems include difficulties in reliably fabricating ever thinner oxide regions for separating the floating gate from both the substrate and the control gate and loss of margin in read and write operations. The loss of margin is a consequence of the fact that the amount of charge that can be stored on the floating gate necessarily decreases as the dimensions of the floating gate are reduced. A reduction in charge makes detection of charge more demanding and is especially problematic in multilevel designs because it becomes increasingly difficult to discriminate states on the basis of charge as the differential in charge between the different states is reduced. Flash memory is also prone to data retention errors due to charge dissipation from the floating gate. Charge dissipation currently limits the cycle life of flash memory and is expected to become more pronounced as scaling continues to smaller dimensions.
Concerns over the future scalability of flash memory have motivated development efforts directed to alternative non-volatile memory technologies. Technologies in the development phase include FeRAM, MRAM, resistive RAM (e.g. memristors), and phase-change memory. In phase-change memory, the memory cell includes a phase-change material as the active memory material and an access device. A phase-change material is a material that exhibits multiple resistance states according to the structural phase of the material. Phase-change materials are reversibly transformable between a high resistance amorphous state and a low resistance crystalline state and can also adopt a continuum of mixed amorphous-crystalline states in which the relative proportions of amorphous phase and crystalline phase content can be varied continuously to provide programming states of intermediate resistance. Chalcogenide materials are one important class of phase-change materials and include a chalcogen element (usually Te and/or Se) along with one or more modifying elements selected from column III (e.g. Ga, In), IV (e.g. Si, Ge or Sn), or V (e.g. As or Sb) of the periodic table. Ge2Sb2Te5, for example, is one of the more common phase-change materials. Further information about phase-change memory may be found in U.S. Pat. Nos. 7,767,992; 7,718,990; 7,706,178; 6,859,390; and 6,671,710; the disclosures of which are hereby incorporated by reference herein.
In order to facilitate commercial adoption of phase-change memory as a replacement for flash memory, it is desirable to exploit as much of the manufacturing infrastructure available for flash memory as possible. In particular, it is desirable to develop a phase-change memory module that is compatible with a flash controller so that phase-change memory can serve as a drop-in replacement for flash memory. In order to achieve this goal, however, it is necessary to develop an error correction scheme for phase-change memory that is within the error correction capability of a standard flash controller. In a typical error correction scheme for flash memory, 16 check bits are used per 512 fetched data bits (sector) to provide an error correction capability of 4-6 bits correctable per sector fetched. Other alternatives are possible or used, such as fetching 64 check bits per 2056 fetched data bits (page).
At the present time, phase-change memory arrays are addressed using a conventional sequential access scheme in which the word line is addressed and remains fixed while the bit lines are sequentially addressed one at a time to read or write a sector (or page). When errors are detected, bad bits are corrected by the controller before passing onto the MPU requesting the read. Within the memory, the bad bits may be left alone or rewritten, or replaced by swapping in a replacement bit or recording the address of the bad bit location in a lookup table and mapping in a corrected data value. Bit replacement typically involves swapping in redundant bits through a fusing process (such as laser fusing) in which a metal line is opened or a dielectric barrier layer is ruptured to form a short, thereby providing a bit state to detect to allow swapping out the bit, row, or column line. Bit replacement, however, is an undesirable process because fusing is time consuming at wafer probe and burdensome in requiring dedicated chip area for redundant bits, thereby increasing the footprint of phase-change memory and wasting space. These aspects tend to raise costs but improve yields, a tradeoff that may be less than favorable. A further negative of fuse repair redundancy is the detection adds to access complexity and can slow performance. And the redundancy is usually not engaged in the field, so bits that deteriorate in the field are not repairable by redundancy, only by ECC. Hence it is desirable to achieve adequate repair of bad bits at the factory and in the field by ECC alone, without redundancy. If major sections can be can be corrected, as in this invention, then the chip can be implemented beneficially with or without redundancy by fuse repair (the fuse repair enhancing correctability, but not being required for commercial chip manufacture).
Adaptation of error correction schemes employed for flash memory to phase-change memory can obviate the need for fuse repair. If the phase-change memory array were free from configuration or addressing defects, implementation of flash-type error correction codes with phase-change memory would be straightforward. In practice, however, errors do occur during manufacturing and defects do arise upon repeated use of the memory. Configuration defects in phase-change memory arrays include short circuits between word lines (e.g. metal to metal shorts), short circuits between bit lines (e.g. metal to metal shorts), short circuits between a word line and a bit line (such as through a shorted memory cell), open circuits along a word line, and open circuits along a bit line.
The presence of short circuit and open circuit defects in phase-change memory complicates adaptation of the conventional error correction codes used in flash controllers because they cause the number of bad bits encountered in the conventional addressing scheme to exceed the capacity of the flash controller to correct errors. When a short circuit or open circuit defect is encountered at a particular word line during a conventional sequential accessing scheme, for example, all or most of a row of memory cells may be rendered unreliable or inaccessible within the sector or page addressed, easily exceeding 100 bits. As a result, the number of memory cells for which data correction is required can readily exceed the capacity of a standard flash controller, usually limited to 4 to 6 depending on the controller company and algorithm used (as is one reasonably familiar with the art).
Although a new controller could be designed specifically for phase-change memory (or other non-volatile memory technologies), it is desirable to avoid the cost and time delay needed to do so. Instead, it is preferable to maintain compatibility with flash memory and to benefit from the existing manufacturing infrastructure for flash memory. There is accordingly a need for alternative memory array technologies that can scale to smaller dimensions while having an error correction capability that manages the number of defective bits to a number within the capability of a standard flash controller.